View PI6ULS5V9306ZEEX_8543870.PDF datasheet online --- IC-ON-LINE

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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| dual bidirectional i 2 c - bu s and smbus voltage - level translator 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 1 pi6uls5v9306 features ? 2 - bit bidirectional translator for sda and scl lines in mixed - mode i2c - bus applications ? standard - mode, fast - mode, and fast - mode plus i2c - bus and smbus compatible ? less than 1.5 ns maximum propagation delay to accommodate standard mode and fast mode i2c - bus devices and multiple masters ? allows voltage level translation between: ? 0.9 v v ref1 and 1.8 v, 2.5 v, 3.3 v or 5 v v ref2 ? 1.2 v v ref1 and 1.8 v, 2.5 v, 3.3 v or 5 v v ref2 ? 1.5 v v ref1 and 2.5 v, 3.3 v or 5 v v ref2 ? 1.8 v v ref1 and 3.3 v or 5 v v ref2 ? 2. 5 v v ref1 and 5 v v ref2 ? 3.3 v v ref1 and 5 v v ref2 ? provides bidirectional voltage translation with no direction pin ? low 3.5 ohm - state connection between input and output ports provides less signal distortion ? open - drain i2c - bus i/o ports (scl1, sda1, scl 2 and sda2) ? 5 v tolerant i2c - bus i/o ports to support mixed - mode signal operation ? high - impedance scl1, sda1, scl2 and sda2 pins for en = low ? lock - up free operation for isolation when en = low ? flow through pin out for ease of printed - circuit board trace rou ting ? esd protection exceeds 4k v hbm per jesd22 - a114 ? package: t dfn2x3 - 8l , m sop - 8l ,soic - 8l ? description the pi6uls5v9306 is a dual bidirectional i 2 c - bus and smbus voltage - level translator with an enable (en) input, and is operational from 1. 0 v to 3. 3 v (v re f1 ) and 1.8 v to 5.5 v(v ref2 ). the pi6uls5v9306 allows bidirectional voltage translations between 1. 0 v and 5 v without the use of a direction pin. the low on - state resistance (ron) of the switch allows connections to be made with minimal propagation delay . when en is high, the translator switch is on, and the scl1 and sda1 i/o are connected to the scl2 and sda2 i/o respectively, allowing bidirectional data flow between ports. when en is low, the translator switch is off, and a high - impedance state exists b etween ports. the pi6uls5v9306 is not a bus buffer that provide s both level translation and physically isolates to ei ther side of the bus when both sides are connected. the pi6uls5v9306 only isolates both sid es when the device is disabled and provides vol tage level translation when active. the pi6uls5v9306 can also be used to run two buses, one at 400 khz operating frequency and the other at 100 khz operating frequency. if the two buses are operating at different frequencies, the 100 khz bus must be isolat ed when the 400 khz operation of the other bus is required. if the master is running at 400 khz, the maximum system operating frequency may be less than 400 khz because of the delays added by the translator. as with the standard i 2 c - bus system, pull - up re sistors are required to provide the logic high levels on the translators bus. the pi6uls5v9306 has a standard open - collector configuration of the i 2 c - bus. the size of these pull - up resistors depends on the system, but each side of the translator must have a pull - up resistor. the device is designed to work with standard - mode, fast - mode and fast mode plus i 2 c - bus devices in addition to smbus devices. when the sda1 or sda2 port is low, the clamp is in the on - state and a low resistance connection exists betwe en the sda1 and sda2 ports. w hen the higher voltage is on the sda2 port , and the sda2 port is high , the voltage on the sda1 port is limited to the voltage set by vref1. when the sda1 port is high, the sda2 port is pulled to the drain pull - up supply voltag e (v dpu ) by the pull - up resistors. this functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. the scl1/scl2 channel also functions as the sda1/sda2 channel. all channel s have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. this is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetric al. the translator provides excellent esd protection to lower voltage devices, and at the same time protects less esd - resistant devices.
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 2 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator pin configuration m sop - 8l /soic - 8l (top view) t dfn2x3 - 8l (top view) pin description pin no name description 1 gnd ground (0 v) 2 vref1 low - voltage side reference supply voltage for scl1 and sda1 3 scl1 serial clock, low - voltage side; connect to vref1 through a pull - up resistor 4 sda1 serial data, low - voltage side; connect to vref1 through a pull - up resistor 5 sda 2 serial data, high - voltage side; connect to vref2 through a pull - up resistor 6 scl 2 serial clock, high - voltage side; connect to vref2 through a pull - up resistor 7 vref 2 hi gh - voltage side reference supply voltage for scl2 and sda2 8 en switch enable input; connect to vref2 and pull - up through a high resistor block diagram figure . 1 block diagram en function h scl1 = scl2; sda1 = sda2 l disabled
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 3 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator maximum ratings storage temperature ................................ ................................ ................... - 6 5 o c to +1 50 o c r eference voltage (2) ................................ ................................ .......................... - 0.5v to + 6.0v reference bias voltage ................................ ................................ ....................... - 0.5v to +6.0 v dc input voltage ................................ ................................ ............................. - 0 .5v to + 6.0 v control input votage(en) ................................ ................................ ............... - 0.5v to +6.0 v channel current (dc) ................................ ................................ ....... 1 28 ma input clamping current ................................ ................................ ..... - 50 ma esd: hbm mode ................................ ................................ ................................ ........... 4 0 00v recommended operation conditions v cc = 2.7 v to 5.5 v; gnd = 0 v; t a = - 40 ? c to +85 ? c ; unless otherwise specified symbol parameter test c onditions min. t yp. max. unit v i/o v oltage on an input/output pin scl1, sda1, scl2, sda2 0 - 5 v v ref1 r eference voltage (1) vref1 0 - 5 v v ref2 r eference bias voltage (2) vref2 0 - 5 v v i (en) i nput voltage on pin en - 0 - 5 v i (pass) p ass switch current - - - 64 ma t a a mbient temperature - - 40 - 85 o c dc electrical characteristics t a = - 40 ? c to +85 ? c ; unless otherwise specified parameter description test conditions (1) min typ. (2) max unit input and output sdab and sclb v ik input clamping voltage i i = - 18 ma; v i(en) = 0 v - - - 1.2 v i ih high - level input current v i = 5 v; v i(en) = 0 v - - 5 a c i(en) input capacitance on pin en v i = 3 v or 0 v - 11 - pf c io(off) off - state input/outp ut capacitance (scln, sdan) v o = 3 v or 0 v; v i(en) = 0 v - 4 - pf c io(on) on - state input/output capacitance (scln, sdan) v o = 3 v or 0 v; v i(en) = 3 v - 10.5 - pf ron on - state resistance (2) (scln, sdan) v i = 0 v; i o = 64 ma v i(en) = 4.5 v - 3.5 5.5 ? i(en) = 3 v - 4.7 7.0 ? i(en) = 2.3 v - 6.3 9.5 ? i(en) = 1.5 v - 60 140 ? i = 2.4v; i o = 15ma v i(en) = 4.5 v 1 6 15 ? i(en) = 3 v 20 60 140 ? i = 1.7 v; i o = 15 ma v i(en) = 2.3 v 20 60 140 ? n otes : 1) all typical values are at t a = 25 c. 2) measured by the voltage drop between the scl1 and scl2, or sda1 and sda2 terminals at the indicated current through the switc h. on - state resistance is determined by the lowest voltage of the two terminals. note: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. t his is a stress rating only and functional operation of the dev ice at these or any other condi tions above those i ndicated in the operational sec tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed.
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 4 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator dynamic characteristics t a = - 40 ? c t o +85 ? c ; unless otherwise specified . values guaranteed by design. symbol parameter c ondition s c l = 50 pf c l = 30 pf c l = 15 pf u nit m in m ax m in m ax m in m ax v i(en) = 3.3 v; v ih = 3.3 v; v il = 0 v; v m = 1.15 v t plh low - to - high propagation delay from (input) scl2 or sda2 to (output) scl1 or sda1 0 0.8 0 0.6 0 0.3 ns t phl high - to - low propagation delay from (input) scl2 or sda2 to (output) scl1 or sda1 0 1.2 0 1 0 0.5 ns v i(en) = 2.5 v; v ih = 3.3 v; v il = 0 v; v m = 0.75 v t plh low - to - high propagatio n delay from (input) scl2 or sda2 to (output) scl1 or sda1 0 1 0 0.7 0 0.4 ns t phl high - to - low propagation delay from (input) scl2 or sda2 to (output) scl1 or sda1 0 1.3 0 1 0 0.6 ns v i(en) = 3.3 v; v ih = 2.3 v; v il = 0 v; v t = 3.3 v; v m = 1.15 v; r l = 3 00 t plh low - to - high propagation delay ffrom (input) scl1 orsda1 to (output) scl2 or sda2 0 0.9 0 0.6 0 0.4 ns t phl high - to - low propagation delay from (input) scl1 or sda1 to (output) scl2 or sda2 0 1.4 0 1.1 0 0.7 ns v i(en) = 2.5 v; v ih = 1.5 v; v il = 0 v; v t = 2.5 v; v m = 0.75 v; r l = 300 t plh low - to - high propagation delay from (input) scl1 orsda1 to (output) scl2 or sda2 0 1 0 0.6 0 0.4 ns t phl high - to - low propagation delay from (input) scl1 or sda1 to (output) scl2 or sda2 0 1.3 0 1.3 0 0.8 ns figure . 2 load circuit for outputs
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 5 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator functional description the pi6uls5v9306 is a dual bidirectional i 2 c - bus and smbus voltage - level translator with an enable (en) input, and is operational from 1. 2 v to 3. 3 v (v ref1 ) and 1.8 v to 5.5 v(v ref2 ). the p i6uls5v9306 allows bidirectional voltage translations between 1.2 v and 5 v without the use of a direction pin. the low on - state resistance (ron) of the switch allows connections to be made with minimal propagation delay. when en is high, the translator sw itch is on, and the scl1 and sda1 i/o are connected to the scl2 and sda2 i/o respectively, allowing bidirectional data flow between ports. when en is low, the translator switch i s off, and a high - impedance state exists between ports. the pi6uls5v9306 is n ot a bus buffer that provide s both level translation and physically isolates to ei ther side of the bus when both sides are connected. the pi6uls5v9306 only isolates both sides when the device is disabled and provides voltage level translation when active. the pi6uls5v9306 can also be us ed to run two buses, one at 400 khz operating frequency and the other at 100 khz operating frequency. if the two buses are operating at different frequencies, the 100 khz bus must be isolated when the 400 khz operation of the other bus is required. if the master is running at 400 khz, the maximum system operating frequency may be less than 400 khz because of the delays added by the translator. as with the standard i 2 c - bus system, pull - up resistors are required to provide the lo gic high levels on the translators bus. the pi6uls5v9306 has a standard open - collector configuration of the i 2 c - bus. the size of these pull - up resistors depends on the system, but each side of the translator must have a pull - up resistor. the device is des igned to work with standard - mode, fast - mode and fast mode plus i 2 c - bus devices in addition to smbus devices. when the sda1 or sda2 port is low, the clamp is in the on - state and a low resistance connection exists between the sda1 and sda2 ports. w hen the h igher voltage is on the sda2 port , and the sda2 port is high, the voltage on the sda1 port is limited to the voltage set by vref1. when the sda1 port is high, the sda2 port is pulled to the drain pull - up supply voltage (v dpu ) by the pull - up resistors. this functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. the scl1/scl2 channel also functions as the sda1/sda2 channel. all channels have the same electrical characterist ics and there is minimal deviation from one output to another in voltage or propagation delay. this is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. the translator provides excellent e sd protection to lower voltage devices, and at the same time protects less esd - resistant devices. a pplication information figure .3 typical open drain application circuit (switch always enabled ) 0.1 f or 0.01 f
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 6 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator figure .4 typical open drain application circuit (swit ch enabled control) open drain application for the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the en input must be connected to vref2 and both pins pulled to high - side vdpu through a pull - u p resistor (typically 200 k?). this allows vref2 to regulate the en input. a filter capacitor on vref2 is recommended. figure .5 typical push - pull application circuit (switch enabled control) push pull application if used in push - pull system, the pull - up resistors on ref side are also needed. the d ata must be unidirectional or the outputs must be 3 - stateable and be controlled by some direction - control mechanism to prevent high - to - low contentions in either direction. 0.1 f or 0.01 f
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 7 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator operating voltage refer to figure 2 min typ (1) max unit v dpu ref2 side pull - up voltage on 200k C the pass through current : i _ pas s i _ pass is determined by the pull - up and the low voltage added on the pi6ls5v9306 in figure 6 , i_pass= (v ref1 - v ol1_9306 )/r pu1 when v_in is 0v, the pi6uls5v9306 can support as large as 64ma pass through current in theory. but we recommend its better t o limit the i_pass in 15ma figure 6 . typical open drain application circuit (1) the sink current : i_sink the device would sink the total current from both pull - up resistors. for example ,in figure bellow, when the sda2 is pulled low by the i2c device, the sink current of the i2c device i_sink=ipass+i_2=i_1+i_2 . the same thing will happen when i2c master pull low the i2c bus. the i_sink should be limited to not larger than the tolerance of the i2c devices. (2) v il ,v ol of the external drive and v ol of pi6uls5v9306 in normal application , the v il of external devices should always be larger than the v ol of pi6uls5v9306. the value of pi6uls5v9306s v ol is determined by the pass through current and the low voltage added on the sda,scl pins. the v ol_ 9306 =v in_l + v up ( v up is mainly determined by the i_pass, it always less than 0.35v.) (3) low vref application the pi6uls5v9306 can support very low vref1 application in theory ,but we recommend not lower than 0.9v . because when vref1 is less than 1.8v, the v ol of ref1 side is a concern in system . for example, in figure 6 , if vref1=0.9v , vdpu=3.3v he v il of the ref1 side i2c master is normally 0.3*vref1 =0.25v, but the v ol of ref2 side can up to 0.1*vdpu=0.36v sometimes. the system designer must mak e sure this situation doesnt happen. a limit for the v ol of ref2 side devices is required then.
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 8 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator the bellow table shows the requirement for v ol of vref2 side devices when using pi6uls5v9306 (requirement for v ol_device in figure 6) the v ol requirement of v ref2 side external devices (temp=25oc, assume the v il of v ref1 side devices is 0.3*v ref1 ) i_pass v ref1 3ma 0. 0. 0. 0. 0. 0. 0. 0. 0.35 0. pull - up resistors and minimum values sizing the pull - up resistor on an open - drain bus is specific to the individual app lication and is dependent on the following driver characteristics: ? the driver sink current ? the v ol of driver ? the v ol of the pi6uls5v9306 ? the v il of the driver ? frequency of operation the following tables can be used to estimate the pull - up resistor value i n different use cases so that the minimum resistance for the pull - up resistor can be found. tables in bellow contain suggested minimum values of pull - up resistors for the pi6uils5v9306 with typical voltage translation levels and drive currents. the calcu lated values assume that both drive currents are the same. v ol = v il = 0.1*vcc and accounts for a 5 % vcc tolerance of the supplies, 1 % resistor values. it should be noted that the resistor chosen in the final application should be equal to or larger tha n the values shown in the tablew to ensure that the pass voltage is less than 10 % of the vcc voltage, and the external driver should be able to sink the total current from both pull - up resistors. pull - up resistor minimum values, 3 ma driver sink current f or pi6uls5v9306 a side b side 1.5v 1.8v 2.5v 3.3v 5.0v 0.9v r pu(a) = 845 pu(b) = 845 pu(a) = 976 pu(b) = 976 pu(a) = none r pu(b) = 887 or both 1.2k pu(a) = none r pu(b) = 1.18k or both 1.5k pu(a) = none r pu(b) = 1.82k or both 2.15k pu(a) = 1.02k pu(b) = 1.02k pu(a) = none r pu(b) = 887 or both 1.3k pu(a) = none r pu(b) = 1.18k or both 1.5k pu(a) = none r pu(b) = 1.82k or both 2.25k pu(a) = none r pu(b) = 866 or both 1.38k pu(a) = none r pu(b) = 1.18k 5k pu(a) = none r pu(b) = 1.78k or both 2.31k pu(a) = 1.47k pu(b) = 1.47k pu(a) = none r pu(b) = 1.15k or both 1.5k pu(a) = none r pu(b) = 1.78k or both 2.42k pu(a) = 1.96k pu(b) = 1.96k pu(a) = none r pu(b) = 1.78k 2.67k pu(a) = none r pu(b) = 1.74k or both 2.95k
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 9 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator pull - up resistor minimum values, 10 ma driver sink current for pi6uls5v9306 a side b side 1.5v 1.8v 2.5v 3.3v 5.0v 0.9v r pu(a) = 255 pu(b) = 255 pu(a) = 287 pu(b) = 287 pu(a) = n one r pu(b) = 267 or both 363 pu(a) = none r pu(b) = 357 or both 449 pu(a) = none r pu(b) = 549 or both 648 pu(a) = 309 pu(b) = 309 pu(a) = none r pu(b) = 267 or both 395 pu(a) = none r pu(b) = 357 or both 481 pu(a) = none r pu(b) = 549 or both 681 pu(a) = none r pu(b) = 261 or both 427 pu(a) = none r pu(b) = 348 or both 506 pu(a) = none r pu(b) = 536 or both 697 pu(a) = 442 pu(b) = 442 pu(a) = none r pu(b) = 348 or both 538 pu(a) = none r pu(b) = 536 th 729 pu(a) = 590 pu(b) = 590 pu(a) = none r pu(b) = 521 or both 782 pu(a) = none r pu(b) = 521 or both 865 pu(a) = 169 pu(b) = 169 pu(a) = 191 pu(b) = 191 pu(a) = none r pu(b) = 178 or both 242 pu(a) = none r pu(b) = 237 or both 302 pu(a) = none r pu(b) = 365 or both 431 pu(a) = 205 pu(b) = 205 pu(a) = none r pu(b) = 178 263 pu(a) = none r pu(b) = 237 or both 323 pu(a) = none r pu(b) = 365 or both 453 pu(a) = none r pu(b) = 174 or both 278 pu(a) = none r pu(b) = 232 or both 337 pu(a) = none r pu(b) = 464 or both 697 pu(a) = 294 pu(b) = 294 pu(a) = none r pu(b) = 232 or both 359 pu(a) = none r pu(b) = 486 or both 729 pu(a) = 392 pu(b) = 392 pu(a) = none r pu(b) = 536 or both 782 pu(a) = none r pu(b) = 348 or both 578
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 10 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator max frequency application the maximum frequ ency is limited by the minimum pulse width low and high as well as rise time and fall time. the rise and fall times are dependent upon translation voltages, the drive strength, the total node capacitance (cl) and the pull - up resistors (rpu ) that are present on the bus. the node capacitance is the addition of the pcb trace capacitance and the device capacitance that exists on the bus. because of the dependency of the external components, pcb layout and the different device operating states the calculation of rise and fall times is complex and has several inflection points along the curve. the main component of the rise and fall times is the rc time constant of the bus line when the device is in its two primary operating states: when device i s in the on state and it is low - impedance, the other is when the device is off isolating the a - side from the b - side. there are some basic guidelines to follow that will help maximize the performance of the device: ? keep trace length to a minimum by placi ng the pi6uls5v9306 close to the processor. ? the signal round trip time on trace should be shorter than the rise or fall time of signal to reduce reflections. ? the faster the edge of the signal, the higher the chance for ringing. ? the higher drive st rength controlled by the pull - up resistor (up to 15 ma), the higher the frequency the device can use. the system designer must design the pull - up resistor value based on external current drive strength and limit the node capacitance (minimize the wire, stu b, connector and trace length) to get the desired operation frequency result.
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 11 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator mechanical information t dfn2x3 - 8(ze) symbol min. max a 0.70 0.80 a1 0.00 0.50 a3 d 1.92 2.08 e 2.92 3.07 d1 1.40 1.60 e1 1.40 1.60 k b 0.20 0.30 e l 0.22 0.38 pkg. dimensions(mm) 0.20ref 0.20min 0.50typ note: ref: jedec mo - 229
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 12 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator recommended land pattern for tdfn2 x 3 - 8l note: all linear dimensions are in millimeters
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 13 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator msop - 8(u)
|||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||| 201 5 - 0 8 - 00 0 6 pt0 45 1 - 5 8 / 1 8 /1 5 14 pi6uls5v9306 dual bidirectional i2c - bus and smbus voltage - level translator soic - 8(w) ordering information part no. p ackage code package pi6uls5v9306 zee x ze lead free and green tdfn2x3 - 8l ,tape & reel pi6uls5v9306 ue u lead free and green m sop - 8l pi6uls5v9306 ue x u lead free and green m sop - 8l ,tape & reel pi6uls5v9306 we w 8 - pin,150 mil wide soic pi6uls5v9306 we x w 8 - pin, 150 mil wide soic , tape & reel note: ? e = pb - free and green ? adding x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom pr oduct. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom .

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